The present invention relates to memory devices, such as dynamic random access memory (DRAM) devices, having row-to-column shorts. In particular, it relates to memory devices having low power consumption after acquiring such shorts and to the methods for achieving such low power consumption.
DRAM devices are a well known type of high-density semiconductor memory used for primary storage (as compared to secondary storage, such as a disk drive) and are often chosen over other memories because of its relative low cost. In exchange for low cost, however, DRAM devices are slower than Static RAM devices, for example, and require periodic refresh operations.
As is known, a DRAM is arranged in an array of rows (often referred to as xe2x80x9cword linesxe2x80x9d) and columns (often referred to as xe2x80x9cdigit linesxe2x80x9d), where the number of rows and columns is usually a power of two. Sometimes, the array is xe2x80x9csquarexe2x80x9d and the number of rows equals the number of columns.
In general, a DRAM array comprises a multiplicity of capacitors to store data. The capacitors are known as cells and each store a single bit of data, either a logic high (1) or a logic low (0). Specifying a particular row and column will address a single memory cell. In the case of a 1024xc3x971024 array (or a 2 to the 10th powerxc3x972 to the 10th power array) a single memory cell would have a 10-bit row address and a 10-bit column address.
All capacitors in the array have an uncommon and common node. The common node is known as a cell plate and has a voltage that is Vcc/2, where Vcc is the voltage supplied to the chip. To store a logic high (1) in a cell, the uncommon node is charged to Vcc through an associated access transistor. To store a logic low (0), the uncommon node (storage node plate) is discharged to ground through the access transistor. A word line (row) signal line is tied to the gate of the access transistor to control access transistor operation.
The data of a cell is read by first equilibrating the cell plate and all digit lines to equilibration voltage Vcc/2. The equilibration voltage is removed and the access transistor for that cell is turned on by supplying an appropriate word line signal. This causes the charge of the capacitor to be dumped to one digit line of a digit line pair. The other digit line of the digit line pairs is used as a reference. If the storage node plate of the capacitor had been charged to Vcc, the voltage on the dumped to digit line of the digit line pairs will increase slightly. Conversely, if the storage node plate had been grounded, the voltage on the digit line will decrease slightly.
The voltage difference between the two digit lines of the digit line pairs is often on the order of 200 mV. Accordingly, the voltage difference is amplified by cross-coupled sense amplifiers (N-sense and P-sense amplifiers) by pulling the digit line with the slightly lower voltage to ground and the digit line with the slightly higher voltage to Vcc. Thereafter, the voltages of the digit line pairs are transferred out of the array to a column decoder and read by an output buffer. This read operation, however, discharges the capacitor of the cell. As such, the same or different logic values are written back to the cell for future use.
Unfortunately, as time passes, the capacitor constituting the cell gradually loses its charge and the data stored therein cannot be accurately read. To prevent data loss, all cells are refreshed periodically in a refresh operation that is similar to a read operation except the data is not actually read. For reference purposes, according to industry standard since about 1970 for a standard DRAM device, a refresh operation occurs about every 15.6 microseconds (refresh rate) for at least one row in an array. Thus, to refresh all rows in a 1024 rowxc3x971024 column array, for example, a complete refresh would take about 16 milliseconds or 15.6 microseconds times 1024 rows.
The two basic means of performing the refresh operation are distributed and burst refresh and each can be accomplished by well known RAS (row address strobe) only refresh, CAS (column address strobe) before RAS refresh, and hidden refresh techniques.
In a distributed refresh, all rows are systematically one-at-a-time refreshed by applying evenly-timed row refresh cycles. In a burst refresh, a series of refresh cycles are performed one right after another until all rows are refreshed and then a lag period exists before refresh beings again. When not being refreshed, distributed refresh allows the DRAM to be written to or read from while burst refresh prevents it. Distributed refresh is the more common refresh of the two.
Since its introduction in 1970, DRAM arrays have become more complex and densely fabricated. As such, the occurrences of electrically shorting rows-to-columns has increased. The principle causes of such shorts includes particle contamination and process variability.
In general, a row-to-column short is a point defect that, as its name implies, electrically shorts together a particular row (word line) to a perpendicular column (digit line). As expected, such shorts ruin integrity of the array. Redundant or spare rows and columns are usually fabricated within the array along with redirection circuitry to substitute functional spare rows and columns for those that are shortedxe2x80x94at least to the extent that shorted rows and columns do not exceed the number of spare rows and columns. Even though this redundancy exists, it is important to realize that the shorted rows and columns are not actually disconnected from the array (this is presently impractical, if not impossible due to the minuscule pitch between rows and columns). They are simply no longer addressed.
Adversely, this creates the potential for biased voltage pull down with the attendant problems of excessive standby current, read/write operations resulting in invalid data and possible damage to good cells in the array. For example, in standby power mode, all word lines (rows) are held to ground while the digit lines (columns) are held to Vcc/2 in anticipation of a new access. But, since the row is shorted to the column in at least one cell, Vcc/2 becomes shorted to ground which results in a much higher standby power mode current than is otherwise necessary or even desired.
Some prior art DRAM devices have used well known xe2x80x9cbleederxe2x80x9d circuits in an attempt to combat this problem. In such a circuit, the amount of current used to hold a digit line to Vcc/2 is limited, thereby limiting power consumption during a short.
This shorting problem further exacerbates itself in DRAM devices having upper and lower or adjacent arrays that are supposed to be electrically isolated from one another. For example, the isolation devices, that serve to isolate one array from the other, trigger a logic high isolation signal during standby power mode times thereby cross-coupling one array to the other (through the sense amplifiers) and, in the event a row-to-column short exists, the standby power mode current leaks twice as much current (which increases power consumption) as it would if the arrays were in fact isolated.
With reference to FIG. 1, a plurality of prior art signal waveforms are shown to illustrate the problem. Word line signal waveform (WL 110) is shown as it sequentially transitions between logic high 112 and logic low 114 values for all array rows (i, i+1, etc.) in both the upper and lower arrays. It will be appreciated that WL 110 is not a single word line signal but a plurality of word line signals, one for each cell, graphically superimposed as one signal. A break 116 in the signal waveform is shown to depict where signal waveforms transition between the upper and lower array during first and second halves of a refresh operation.
Correspondingly, the isolation signal for the upper array (ISO Upper 113) is logic high 112 during the time interval from time 118 to before time 128 when the word line signal waveform WL 110 transitions to activity in the lower array. It is logic low 114 during the time 128 to the time 130 and during the time 132 to time 134, for example, when the word line signal waveform WL 110 is logic high 112 for the lower array thereby electrically isolating the upper array therefrom. However, during the times when the word line signal waveform WL 110 is logic low 114 in the lower array during all times of standby power mode between time 130 and time 132 and between time 134 and 136, for example, the ISO Upper 113 goes logic high (in a well known bootstrap signal 140 manner). As a result, the upper array is no longer isolated from the lower array and, if a row-to-column short exists, standby power mode current leaks twice as much current as it would if the arrays were in fact isolated. Moreover, the switching current necessary to drive the ISO Upper signal line to a bootstrapped logic high during such times is additionally wasted current.
In a similar manner, the isolation signal for the lower array (ISO Lower 115) is logic high 112 during the time interval from before time 128 to time 136 and beyond when the word line signal waveform WL 110 transitions from activity in the upper to the lower array. It is logic low 114 during the time 118 to the time 120 and during the time 122 to time 124, for example, when the word line signal waveform WL 110 is logic high 112 for the upper array thereby electrically isolating the lower array therefrom. However, during the times when the word line signal waveform WL 110 is logic low 114 in the upper array during all times of standby power mode between time 120 and time 122 and between time 124 and 126, for example, the ISO Lower 115 goes logic high (in a well known bootstrap signal 140 manner). As a result, the lower array is no longer isolated from the upper array and, if a row-to-column short exists, standby power mode current leaks twice as much current as it would if the arrays were in fact isolated. Moreover, the switching current necessary to drive the ISO Lower signal line to a bootstrapped logic high during such times is additionally wasted current.
As DRAM devices continue to grow even denser, the above-identified row-to-column short problems are sure to correspondingly increase. Accordingly, present and future memory devices desire solutions for standby power mode current leakage without suffering a related wafer space penalty.
The above-mentioned and other problems become solved by applying the apparatus, method and system principles and teachings associated with the hereinafter described low power consumption memory devices having row-to-column shorts.
In one embodiment an isolation signal line in a memory device having a standby power mode is configured to be exclusively held as either a logic high or logic low during some portion of the standby power mode, such as in a self refresh, and as the other of the logic high and logic low during another portion of the standby power mode. In this manner, the isolation signal line is prevented from switching from a logic low to a logic high every time the memory device operates in standby power mode. As a result, memory devices having an upper and lower array achieve true electrical isolation during standby power modes and, if a row-to-column short exists, standby power mode current leakage is cut in half as compared to non-isolated arrays. Moreover, the switching current necessary to drive the isolation signal line to a bootstrapped logic high during such standby power mode times is prevented. Thus, low power consumption in the memory device is achieved.
In another embodiment, an isolation signal line in a memory device is configured to be held as either a logic high or logic low during a first portion of a refresh operation and as the other of the logic high and logic low during a second portion of the refresh operation. In one embodiment, the first and second portions of the refresh operation correspond to first and second halves of a refresh operation where the upper and then lower array is refreshed.
In still another embodiment, methods for achieving low power consumption in memory devices executing standby power modes, refresh operations and read operations are taught. Electronic systems, wafers, and DRAM devices are also described.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.